Completeness of Flat Coalgebraic Fixpoint Logics

Modal fixpoint logics traditionally play a central role in computer science, in particular in artificial intelligence and concurrency. The mu-calculus and its relatives are among the most expressive logics of this type. However, popular fixpoint logics tend to trade expressivity for simplicity and readability, and in fact often live within the single variable fragment of the mu-calculus. The family of such flat fixpoint logics includes, e.g., LTL, CTL, and the logic of common knowledge. Extending this notion to the generic semantic framework of coalgebraic logic enables covering a wide range of logics beyond the standard mu-calculus including, e.g., flat fragments of the graded mu-calculus and the alternating-time mu-calculus (such as alternating-time temporal logic ATL), as well as probabilistic and monotone fixpoint logics. We give a generic proof of completeness of the Kozen-Park axiomatization for such flat coalgebraic fixpoint logics.Comment: Short version appeared in Proc. 21st International Conference on Concurrency Theory, CONCUR 2010, Vol. 6269 of Lecture Notes in Computer Science, Springer, 2010, pp. 524-53

Propositional Dynamic Logic with Converse and Repeat for Message-Passing Systems

The model checking problem for propositional dynamic logic (PDL) over message sequence charts (MSCs) and communicating finite state machines (CFMs) asks, given a channel bound $B$, a PDL formula $\varphi$ and a CFM $\mathcal{C}$, whether every existentially $B$-bounded MSC $M$ accepted by $\mathcal{C}$ satisfies $\varphi$. Recently, it was shown that this problem is PSPACE-complete. In the present work, we consider CRPDL over MSCs which is PDL equipped with the operators converse and repeat. The former enables one to walk back and forth within an MSC using a single path expression whereas the latter allows to express that a path expression can be repeated infinitely often. To solve the model checking problem for this logic, we define message sequence chart automata (MSCAs) which are multi-way alternating parity automata walking on MSCs. By exploiting a new concept called concatenation states, we are able to inductively construct, for every CRPDL formula $\varphi$, an MSCA precisely accepting the set of models of $\varphi$. As a result, we obtain that the model checking problem for CRPDL and CFMs is still in PSPACE

GPU Accelerated counterexample generation in LTL model checking

Strongly Connected Component (SCC) based searching is one of the most popular LTL model checking algorithms. When the SCCs are huge, the counterexample generation process can be time-consuming, especially when dealing with fairness assumptions. In this work, we propose a GPU accelerated counterexample generation algorithm, which improves the performance by parallelizing the Breadth First Search (BFS) used in the counterexample generation. BFS work is irregular, which means it is hard to allocate resources and may suffer from imbalanced load. We make use of the features of latest CUDA Compute Architecture-NVIDIA Kepler GK110 to achieve the dynamic parallelism and memory hierarchy so as to handle the irregular searching pattern in BFS.We build dynamic queue management, task scheduler and path recording such that the counterexample generation process can be completely finished by GPU without involving CPU. We have implemented the proposed approach in PAT model checker. Our experiments show that our approach is effective and scalable. ?Springer International Publishing Switzerland 2014.EI0413-429882

Asynchronous Games over Tree Architectures

We consider the task of controlling in a distributed way a Zielonka asynchronous automaton. Every process of a controller has access to its causal past to determine the next set of actions it proposes to play. An action can be played only if every process controlling this action proposes to play it. We consider reachability objectives: every process should reach its set of final states. We show that this control problem is decidable for tree architectures, where every process can communicate with its parent, its children, and with the environment. The complexity of our algorithm is l-fold exponential with l being the height of the tree representing the architecture. We show that this is unavoidable by showing that even for three processes the problem is EXPTIME-complete, and that it is non-elementary in general

Propositional Dynamic Logic for Message-Passing Systems

We examine a bidirectional propositional dynamic logic (PDL) for finite and infinite message sequence charts (MSCs) extending LTL and TLC-. By this kind of multi-modal logic we can express properties both in the entire future and in the past of an event. Path expressions strengthen the classical until operator of temporal logic. For every formula defining an MSC language, we construct a communicating finite-state machine (CFM) accepting the same language. The CFM obtained has size exponential in the size of the formula. This synthesis problem is solved in full generality, i.e., also for MSCs with unbounded channels. The model checking problem for CFMs and HMSCs turns out to be in PSPACE for existentially bounded MSCs. Finally, we show that, for PDL with intersection, the semantics of a formula cannot be captured by a CFM anymore

Quantification of tackling demands in elite Australian football using integrated wearable athlete technology

Paper cited in abstract - ECSS 2012 : 17th Annual Congress of the European College of Sport Science Book of Abstracts --- European College of Sport Science (Cologne, Germany) - 9789090268682, page 28

Validation of accelerometer data for measuring impacts during jumping and landing tasks

The purpose of this study was to examine the validity of a commercially-available accelerometer, as used in the field team sports context. Ten adult participants completed two movement tasks: 1) a drop landing task from 30-cm, 40-cm and 50-cm heights [DLAND], and 2) a countermovement jumping task [CMJ]. Peak acceleration values, both smoothed and unsmoothed, occurring in the longitudinal axis [Y] and calculated to produce vector magnitude values [VM], were compared to peak vertical ground reaction force values [VGRF]. All acceleration measures were moderately correlated (r = 0.45 &ndash; 0.70), but also significantly higher than weight-adjusted VGRF, for both tasks. Though the raw acceleration measures were mostly above the acceptable limit for error (&gt; 20%), the smoothed data had reduced error margins by comparison, most of which were well below 20%. These results provide some support for the continued use of accelerometer data, particularly when smoothed, to accurately quantify impacts in the field.<br /

VALIDATION OF ACCELEROMETER DATA FOR MEASURING IMPACTS DURING JUMPING AND LANDING TASKS

The purpose of this study was to examine the validity of a commercially-available accelerometer, as used in the field team sports context. Ten adult participants completed two movement tasks: 1) a drop landing task from 30-cm, 40-cm and 50-cm heights [DLAND], and 2) a countermovement jumping task [CMJ]. Peak acceleration values, both smoothed and unsmoothed, occurring in the longitudinal axis [Y] and calculated to produce vector magnitude values [VM], were compared to peak vertical ground reaction force values [VGRF]. All acceleration measures were moderately correlated (r = 0.45 – 0.70), but also significantly higher than weight-adjusted VGRF, for both tasks. Though the raw acceleration measures were mostly above the acceptable limit for error (> 20%), the smoothed data had reduced error margins by comparison, most of which were well below 20%. These results provide some support for the continued use of accelerometer data, particularly when smoothed, to accurately quantify impacts in the field

Analog Property Checkers: A Ddr2 Case Study

The formal specification component of verification can be exported to simulation through the idea of property checkers. The essence of this approach is the automatic construction of an observer from the specification in the form of a program that can be interfaced with a simulator and alert the user if the property is violated by a simulation trace. Although not complete, this lighter approach to formal verification has been effectively used in software and digital hardware to detect errors. Recently, the idea of property checkers has been extended to analog and mixed-signal systems. In this paper, we apply the property-based checking methodology to an industrial and realistic example of a DDR2 memory interface. The properties describing the DDR2 analog behavior are expressed in the formal specification language stl/psl in form of assertions. The simulation traces generated from an actual DDR2 interface design are checked with respect to the stl/psl assertions using the amt tool. The focus of this paper is on the translation of the official (informal and descriptive) specification of two non-trivial DDR2 properties into stl/psl assertions. We study both the benefits and the current limits of such approach